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RM0008
2.3
Table 1.
Memory and bus architecture
Memory map
See the datasheet corresponding to your device for a comprehensive diagram of the
memory map. Table 1 gives the boundary addresses of the peripherals available in all
STM32F10xxx devices.
Register boundary addresses
Boundary address
Peripheral
Bus
Register map
0x5000 0000 - 0x5000 03FF
0x4003 0000 - 0x4FFF FFFF
0x4002 8000 - 0x4002 9FFF
0x4002 3400 - 0x4002 7FFF
0x4002 3000 - 0x4002 33FF
0x4002 2000 - 0x4002 23FF
0x4002 1400 - 0x4002 1FFF
0x4002 1000 - 0x4002 13FF
0x4002 0800 - 0x4002 0FFF
0x4002 0400 - 0x4002 07FF
0x4002 0000 - 0x4002 03FF
0x4001 8400 - 0x4001 7FFF
0x4001 8000 - 0x4001 83FF
0x4001 4000 - 0x4001 7FFF
0x4001 3C00 - 0x4001 3FFF
0x4001 3800 - 0x4001 3BFF
0x4001 3400 - 0x4001 37FF
0x4001 3000 - 0x4001 33FF
0x4001 2C00 - 0x4001 2FFF
0x4001 2800 - 0x4001 2BFF
0x4001 2400 - 0x4001 27FF
USB OTG FS
Reserved
Ethernet
Reserved
CRC
Flash memory interface
Reserved
Reset and clock control RCC
Reserved
DMA2
DMA1
Reserved
SDIO
Reserved
ADC3
USART1
TIM8 timer
SPI1
TIM1 timer
ADC2
ADC1
AHB
AHB
Section 26.14.6 on page 778
Section 27.8.5 on page 946
Section 3.4.4 on page 52
Section 6.3.11 on page 102
Section 10.4.7 on page 196
Section 10.4.7 on page 196
Section 20.9.16 on page 510
Section 11.12.15 on page 231
Section 25.6.8 on page 693
Section 13.4.21 on page 317
Section 23.5 on page 614
Section 13.4.21 on page 317
Section 11.12.15 on page 231
Section 11.12.15 on page 231
0x4001 2000 - 0x4001 23FF
0x4001 1C00 - 0x4001 1FFF
0x4001 1800 - 0x4001 1BFF
0x4001 1400 - 0x4001 17FF
0x4001 1000 - 0x4001 13FF
0x4001 0C00 - 0x4001 0FFF
0x4001 0800 - 0x4001 0BFF
0x4001 0400 - 0x4001 07FF
0x4001 0000 - 0x4001 03FF
GPIO Port G
GPIO Port F
GPIO Port E
GPIO Port D
GPIO Port C
GPIO Port B
GPIO Port A
EXTI
AFIO
Doc ID 13902 Rev 9
APB2
Section 8.5 on page 167
Section 8.5 on page 167
Section 8.5 on page 167
Section 8.5 on page 167
Section 8.5 on page 167
Section 8.5 on page 167
Section 8.5 on page 167
Section 9.3.7 on page 181
Section 8.5 on page 167
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